Mitigation of runaway programming of a memory device

ABSTRACT

Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/191,523 (allowed), filed Aug. 14, 2008 and titled “MITIGATION OFRUNAWAY PROGRAMMING OF A MEMORY DEVICE,” which is commonly assigned andincorporated by reference in its entirety herein.

TECHNICAL FIELD

The present invention relates generally to memory devices and in aparticular embodiment the present invention relates to non-volatilememory devices.

BACKGROUND

Memory devices can include internal, semiconductor, integrated circuitsin computers or other electronic devices. There are many different typesof memory including random-access memory (RAM), read only memory (ROM),dynamic random access memory (DRAM), static RAM (SRAM), synchronousdynamic RAM (SDRAM), and flash memory.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Common uses for flash memory include personal computers, personaldigital assistants (PDAs), digital cameras, and cellular telephones.Program code and system data such as a basic input/output system (BIOS)are typically stored in flash memory devices for use in personalcomputer systems.

During a typical prior art programming operation of a flash memory cell,a selected word line coupled to the selected memory cell to beprogrammed is biased with a series of incrementing voltage programmingpulses that start at an initial voltage that is greater than apredetermined programming voltage (e.g., approximately 16V). Theprogramming pulse increases a charge level, thereby increasing thecell's threshold voltage V_(t), on a floating gate of the memory cell.

A verify operation is performed after each programming pulse todetermine if the cell's threshold voltage has increased to the targetprogram level. FIG. 1 shows typical programming and program verifypulses. The programming pulses 101, 102 are incrementally increasingvoltage pulses that start at a certain programming voltage (e.g., 16V)and increase by a step voltage 104 for every subsequent programmingpulse. The programming pulses bias the selected word lines beingprogrammed and are repeated until the memory cells being programmed passa program verify operation. Each programming pulse increases thethreshold voltage of the selected memory cells.

A verify pulse 100, 103 is typically a ramp voltage that biases theselected word lines between each programming pulse. The memory cells onthe selected word line turn on when the ramp voltage reaches thethreshold voltage to which the cells have been programmed. A currentflows on the bit lines coupled to the memory cells being programmed whenthe memory cells turn on. This current flow is detected by senseamplifiers that indicate to comparison circuitry that a comparisonoperation should be performed to determine if the data stored in thememory cell is equal to the target data.

One problem with this method of program verification is that it does nottake into account when the memory cell has been over-programmed.Over-programming results from a memory cell being under-programmed afterone program pulse and the next program pulse causes the cell's thresholdvoltage to exceed the target threshold voltage.

FIG. 8 illustrates a typical prior art programming operation with L0-LNprogramming levels. It is assumed that L4 is the target V_(t) 801. Asthe memory cell is being programmed, its threshold voltage isincremented in programming steps 803 towards the target V_(t) 801. Whenthe threshold voltage is substantially close 805 to L4, the equal-tocomparator inhibits further programming.

Since the prior art program verification relies only on the targetthreshold voltage and the programmed threshold voltage beingsubstantially equal to each other, once the cell's threshold voltageexceeds the target range, the two can no longer be equal and theselected memory cell continues to fail program verify operations. Thisresults in additional programming pulses being issued to the memory cellthus resulting in runaway programming of that memory cell. The runawayprogramming is illustrated in FIG. 9.

Of the programming levels L0-LN, L4 is again assumed to be the target901 programming level. The memory cell is programmed in larger thresholdvoltage programming steps 903. The threshold voltage step 907 prior tothe L4 target does not quite reach the target threshold voltage 901.Thus, the next programming operation moves the threshold voltage pastthe L4 target. Another verify operation with an “equal-to” comparator atthis point results in the threshold voltage being found not to be equalto the target threshold voltage. Programming of the memory cellcontinues, even though the threshold voltage is past the target 901voltage, since the verify operation failed the “equal-to” comparison.

One method for reducing runaway programming is to use smallerincremental increases of the programming pulses from one programmingpulse to the next. However, this results in degraded performance sincethe programming would require more time to reach the target thresholdvoltage.

For the reasons stated above, and for other reasons stated below thatwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art toreduce runaway programming of memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows typical program and program verify pulses.

FIG. 2 shows a block diagram of a circuit for performing a programverify operation in accordance with one embodiment of the method formitigation of runaway programming.

FIG. 3 shows schematic diagram of one embodiment of a portion of amemory array in accordance with the memory array of FIG. 2.

FIG. 4 shows a schematic diagram of one embodiment of a circuit forperforming a greater-than-or-equal-to comparison in accordance with themethod for mitigation of runaway programming.

FIG. 5 shows a flowchart of one embodiment of a method for reducingrunaway programming in a memory device in accordance with the embodimentof FIG. 4.

FIG. 6 shows block diagram of one embodiment of a memory system thatincorporates the method for quick charge loss compensation.

FIG. 7 shows a block diagram of a circuit of an alternate embodiment forperforming a program verify operation in accordance with one embodimentof the method for mitigation of runaway programming.

FIG. 8 shows typical prior art programming levels.

FIG. 9 shows typical prior art programming levels experiencing runawayprogramming.

FIG. 10 shows programming levels in accordance with the method of FIG.5.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

FIG. 2 illustrates one example of a circuit that performs a non-volatilememory program verify using the greater-than-or-equal-to comparisonoperation of the present embodiments. The memory array 200 comprises aplurality of non-volatile memory cells organized in rows and columns.Data lines (e.g., bit lines) are connected to the columns of memorycells that are also coupled to the column multiplexer 201. Access lines(e.g., word lines) are coupled to the control gates of the rows ofmemory cells (wherein the control gates themselves may make up the wordline). One example of a non-volatile memory array is illustrated in FIG.3 and discussed subsequently.

A digital counter 209 generates a digital count that is converted by adigital-to-analog converter (DAC) and ramp voltage generator 211 to ananalog signal (ramp voltage). In one embodiment, the digital counter 209is configured to count from 0 to 255.

The ramp voltage is input to the row decoder 213 during a program verifyoperation. The ramp voltage biases the selected word lines that arebeing programmed. When the ramp voltage reaches the threshold voltage towhich the selected memory cell or cells are programmed, the selectedmemory cells programmed to that voltage turn on and current begins toflow in the bit lines coupled to the selected memory cells. The senseamplifiers 204, through the column multiplexer 201, sense the currentand generate a signal indicating that the selected memory cells haveturned on.

When a program operation begins, the target data to which the memorycells are to be programmed are stored in the data latches 206. When thesense amplifier 204 indicates that the selected memory cells have turnedon, a comparison is performed, by a greater-than-or-equal-to comparator208, between the digital count that caused the memory cells to turn onand the target data that was stored in the data latches 206 at thebeginning of the programming operation. FIG. 4, as describedsubsequently, illustrates one embodiment of a greater-than-or-equal-tocomparator circuit of the present embodiment. When thegreater-than-or-equal-to comparator 208 indicates that the programmeddata is equal to or greater than the target data, a successfulprogramming operation indication is generated that stops additionalprogramming pulses.

FIG. 7 illustrates an alternate embodiment of a circuit for performing anon-volatile program verify using the greater-than-or-equal-tocomparison operation. This embodiment uses the same memory array 700,column multiplexer 701, sense amplifier 704, data latches 706, and rowdecoder 713 of FIG. 2.

The embodiment of FIG. 7 uses an analog ramp generation circuit 709 thatgenerates an analog ramp signal. The analog ramp signal is input to ananalog-to-digital converter (ADC) 702. The output of the ADC 702 is adigital signal representative of the ramp signal. This digital signal isthen used by the greater-than-or-equal-to comparator circuit 708 asdescribed subsequently with reference to FIG. 4.

FIG. 3 illustrates a schematic diagram of a portion of a NANDarchitecture memory array 301 comprising series strings of non-volatilememory cells on which one embodiment of the method for charge losscompensation can operate. While the subsequent discussions refer to aNAND memory device, the present embodiments are not limited to such anarchitecture but can be used in other memory device architectures aswell.

The array is comprised of an array of non-volatile memory cells 301(e.g., floating gate) arranged in columns such as series strings 304,305. Each of the cells 301 are coupled drain to source in each seriesstring 304, 305. A word line WL0-WL31 that spans across multiple seriesstrings 304, 305 is connected to the control gates of each memory cellin a row in order to bias the control gates of the memory cells in therow. The bit lines BL1, BL2 are eventually connected to sense amplifiers(not shown) that detect the state of each cell by sensing current on aparticular bit line.

Each series string 304, 305 of memory cells is coupled to a source line306 by a source select gate 316, 317 and to an individual bit line BL1,BL2 by a drain select gate 312, 313. The source select gates 316, 317are controlled by a source select gate control line SG(S) 318 coupled totheir control gates. The drain select gates 312, 313 are controlled by adrain select gate control line SG(D) 314.

Each memory cell can be programmed as a single level cell (SLC) ormultilevel cell (MLC). Each cell's threshold voltage (V_(t)) isindicative of the data that is stored in the cell. For example, in anSLC, a V_(t) of 0.5V might indicate a programmed cell while a V_(t) of−0.5V might indicate an erased cell. The MLC may have multiple V_(t)ranges that each indicate a different state. Some multilevel cells takeadvantage of the analog nature of a traditional flash cell by assigninga bit pattern to a specific voltage range stored on the cell. Thistechnology permits the storage of two or more bits per cell, dependingon the quantity of voltage ranges assigned to the cell.

FIG. 4 illustrates a schematic diagram of one embodiment of a comparatorcircuit 208 for performing a greater-than-or-equal-to comparison inaccordance with the method for mitigation of runaway programming. Thiscircuit is for purposes of illustration only as thegreater-than-or-equal-to comparison discussed previously with referenceto FIG. 2 can be performed using other circuits or in software that isexecuted by a control circuit.

The circuit 208 of FIG. 4 is comprised of a comparison circuit thatincludes eight equal-to circuits 400-407 and eight greater-than circuits440-447. The circuit 208 additionally has two sense amplifier controlsignal transistors 430, 432, and a program verify control transistor431. An inverter circuit 420 inverts an input from the comparisoncircuit and outputs that signal as the MATCH signal. In the illustratedembodiment, a MATCH signal of logical 1 indicates that the comparison ofDx (i.e., D7-D0) with Qx (i.e., Q7-Q0) has resulted in Dx being greaterthan or equal to Qx. A MATCH signal of logical 0 indicates that this isnot true. An alternate embodiment can reverse this logic.

The greater-than-or-equal-to comparison performs a most-significant bitto least-significant bit comparison on a bit-by-bit basis. Thecomparison circuit portion of FIG. 4 is comprised of eight bit“equal-to” comparison circuits 400-407 that are each comprised of fourtransistors. The inputs D7-D0 are the count signal data from the digitalcounter circuit 209 of FIG. 2. The inputs D7 - D0 are the inverse of thecount signal data from the digital counter circuit 209. The inputs Q7-Q0are the target data from the data latch 206 of FIG. 2. The inputs Q7 -Q0 are the inverse of the target data from the data latch 206.

The “equal-to” comparison circuits 400-407 compare Dx to Qx to determineif these two signals are equal. If they are equal, at least one side ofthe comparison circuits 400-407 will be turned on.

Additional circuitry 440-447 is coupled to each “equal-to” bitcomparison circuits 400-407. These circuits 440-447 are “greater-than”comparison circuits that performs a simple logical 1 to logical 0comparison with Dx and Qx. In other words, when Dx and Qx are equal,these circuits 440-447 are off. Also, when Qx is greater than Dx, thesecircuits 440-447 are off. However, when Dx is greater than Qx, at leastone of these circuits 440-447 is on and pulling the input to theinverter circuit 420 to ground through a control transistor that isenabled by a logical high pulse on the SENSE AMP OUT signal. Thus, MATCHwill be a logical 1.

The equal-to comparisons of the comparison circuit 208 of FIG. 4propagate through from the top MSB circuit 400 to the bottom LSB circuit407. At any point along the comparison, if the bits are equal the node470 is discharged to ground and the comparison is stopped since furthercomparisons are not necessary.

As one example of operation, assume that Dx is “010000” and that Qx is“000100” so that Dx is greater than Qx. Prior to the program verifyoperation, SENSE AMP OUT is at a logical low state so that the topcontrol transistor is turned on to precharge the input to the invertercircuit 420 to V_(CC) (i.e., a logical 1 state). Thus, MATCH is at alogical 0 state. A logical high pulse on the SENSE AMP OUT signalindicates that current has been detected on the bit line of the memorycell being program verified. As discussed previously, this indicatesthat the Dx count has generated a threshold voltage of sufficientmagnitude to turn on the memory cell causing it to conduct and producethe bit line current. Thus the top control transistor 430 is turned offwhen the SENSE AMP OUT signal goes high and the bottom controltransistor 432 is turned on.

Starting at the MSB of each series of bits, both D7 and Q7 are 0.Therefore, the first “equal-to” circuit 400 will be turned on since D7and Q7 are both logical ones and the transistors with those signalinputs will be on.

The next bits, D6=1 and Q6=0, are then compared. Since these bits arenot equal, the D6/Q6 “equal-to” circuit 401 is not turned on. However,the D6/Q6 “greater-than” circuit 441 is turned on since D6 is greaterthan Q6. This is true because the D6 transistor is turned on by thelogical 1 of D6 and the Q6 transistor is turned on by the logical 1 ofQ6 . This pulls the top node 450 of the comparison portion of thecircuit to ground. If the PGMVFY is a logical 1, indicating that aprogram verify operation is being performed, the ground potential isapplied to the input of the inverter circuit 420. Once inverted, theMATCH signal is now a logical 1 indicating that Dx isgreater-than-or-equal-to Qx. The state of the remaining bits of the Dxand Qx series of bits is not relevant since the top node is alreadypulled to ground.

In another example of operation, assume that Dx is “100000” and Qx is“110100” so that Qx is greater than Dx. The D7 and Q7 bits of eachseries of bits are equal. Thus, the first “equal-to” comparison circuit400 is turned on. The D6 and Q6 bits of each series of bits are notequal since D6=0 and Q6=1. Thus, the second “equal-to” comparisoncircuit 401 is not turned on. The “greater-than” D6/Q6 circuit 441 isalso not turned on. Since D6=0, the top transistor of this circuit 441is off and the top node 450 of the circuit is not pulled to ground. TheMATCH output signal remains at a logical 0 since the input of theinverter circuit 420 is still precharged to V_(CC).

As a final example of operation, if Dx and Qx are both equal it can beseen from the above examples that all of the “equal-to” comparisoncircuits 400-407 will be turned on. Since the lower control transistor432 is turned on when the SENSE AMP OUT signal is high, this transistor432 is on so that the top node 450 of the circuit is pulled to ground.Because a program verify operation is being performed, PGMVFY is high toturn on its respective transistor 431 so that the input of the invertercircuit 420 is at a logical 0 state. Thus, the MATCH output signal goesto a logical 1 state indicating that D7-D0 are equal to Q7-Q0.

FIG. 5 illustrates a flowchart of one embodiment of a method formitigating runaway programming in a memory device in accordance with thecomparison circuit of FIG. 4. A programming algorithm is initiated 500.An initial indication of a program verify operation occurring isdetected 501. This indication can be the PGMVFY signal going to alogical high, the SENSE AMP OUT signal going to a logical high, or acombination of the occurrence of these two signals.

When the selected memory cell turns on, the digital count signalresponsible for generating the verify voltage that caused the memorycell to turn on is determined 502. Also at this point, the target datastored in the memory latches is also read.

The Dx and Qx bit strings are then compared from MSB to LSB 503. Thiscan be accomplished by the comparison circuit of FIG. 4 or by some othermeans. If the comparison shows that Dx is greater-than-or-equal-to Qx505, the MATCH signal is generated to indicate that this condition istrue. If Dx is less than Qx, the MATCH signal indicates 509 that the Dxand Qx signals are not greater-than-or-equal-to each other. In thiscase, additional programming is necessary and another programmed pulseis generated 511 to further increase the threshold voltage of theselected memory cell or cells and the program verify process isrepeated.

FIG. 10 illustrates the results of the programming method of FIG. 5 asapplied to programming levels L0-LN. In this example, it is assumed thatL4 is the target V_(t) 1001. As the programming pulses bias the selectedmemory cell, its threshold voltage is moved in steps 1003 from theerased level upward. At the point 1005 where the threshold voltage isclose to the target level 1001, it will still fail the verify operationsince the threshold voltage is less than the target threshold. The nextprogramming pulse will cause the threshold voltage to increase to L5.However, the greater-than-or-equal-to comparator will inhibit furtherprogramming since the threshold voltage is now greater than the targetthreshold voltage 1001.

FIG. 6 illustrates a functional block diagram of a memory device 600.The memory device 600 is coupled to an external controller 610. Thecontroller 610 may be a microprocessor or some other type of controlcircuitry. The memory device 600 and the controller 610 form part of amemory system 620. The memory device 600 has been simplified to focus onfeatures of the memory that are helpful in understanding the presentembodiments.

The memory device 600 includes an array 630 of non-volatile memorycells, such as the one illustrated previously in FIG. 3. The memoryarray 630 is arranged in banks of word line rows and bit line columns.In one embodiment, the columns of the memory array 630 are comprised ofseries strings of memory cells. As is well known in the art, theconnections of the cells to the bit lines determines whether the arrayis a NAND architecture, an AND architecture, or a NOR architecture.

Address buffer circuitry 640 is provided to latch address signalsprovided through the I/O circuitry 660. Address signals are received anddecoded by a row decoder 644 and a column decoder 646 to access thememory array 630. It will be appreciated by those skilled in the art,with the benefit of the present description, that the number of addressinput connections depends on the density and architecture of the memoryarray 630. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

The memory device 600 reads data in the memory array 630 by sensingvoltage or current changes in the memory array columns using senseamplifier circuitry 650. The sense amplifier circuitry 650, in oneembodiment, is coupled to read and latch a row of data from the memoryarray 630. Data input and output buffer circuitry 660 is included forbidirectional data communication as well as address communication over aplurality of data connections 662 with the controller 610. Writecircuitry 655 is provided to write data to the memory array.

Memory control circuitry 670 decodes signals provided on controlconnections 672 from the processor 610. These signals are used tocontrol the operations on the memory array 630, including data read,data write (program), and erase operations. The memory control circuitry670 may be a state machine, a sequencer, or some other type ofcontroller to generate the memory control signals. In one embodiment,the memory control circuitry 670 is configured to execute theprogramming method of the present embodiments that mitigates runawayprogramming in the memory device.

The flash memory device illustrated in FIG. 6 has been simplified tofacilitate a basic understanding of the features of the memory. A moredetailed understanding of internal circuitry and functions of flashmemories are known to those skilled in the art.

CONCLUSION

In summary, one or more embodiments mitigate runaway programming of amemory device. The digital counter output signal, that is used togenerate a program verify voltage, is compared to the target data storedin the data latch during programming. If the digital counter outputsignal is greater-than-or-equal-to the target data when thecorresponding sense amplifier turns on, a match indication is generated.Otherwise, additional programming is performed. The program run awayinhibit scheme enables use of advanced signal processing such as TCM &LDPC for data correction. This is because, even when correct programlevels are not reached while programming, the program levels in errorare close to the correct target levels.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A method for programming a memory device, the method comprising:generating a verify voltage responsive to a count wherein the verifyvoltage is configured to activate a memory cell; and generating anindication signal when the count is greater than or equal to target datastored in the memory cell.
 2. The method of claim 1 and furthercomprising storing the target data in data latches.
 3. The method ofclaim 2 wherein generating the indication signal comprises comparing thetarget data stored in the data latches to the count that causes thememory cell to activate.
 4. The method of claim 1 wherein the verifyvoltage is a ramped voltage signal.
 5. The method of claim 4 wherein theramped voltage signal is generated from a digital-to-analog converterconverting the count into an analog signal.
 6. The method of claim 1wherein current in a data line coupled to the memory cell is detected todetermine when the memory cell has been activated.
 7. The method ofclaim 1 and further comprising: applying a programming pulse to thememory cell prior to the verify voltage; and halting additionalprogramming pulses to the memory cell responsive to the indicationsignal.
 8. A method for programming a memory device, the methodcomprising: storing, to a latch, target data to which a memory cell isto be programmed; applying a programming pulse to the memory cell; andperforming a program verify operation on the memory cell after theprogramming pulse, the program verify operation comprising: biasing thememory cell with a ramped voltage signal; generating a digitalrepresentation of the ramped voltage signal; detecting when the memorycell is activated responsive to a particular voltage of the rampedvoltage signal; and generating a program verify indication when thedigital representation of the particular voltage is greater than orequal to the latch target data.
 9. The method of claim 8 wherein ananalog-to-digital converter is configured to convert the ramped voltagesignal to the digital representation of the ramped voltage signal. 10.The method of claim 8 wherein applying the programming pulse comprisesapplying a series of programming pulses to the memory cell wherein eachsubsequent programming pulse is incrementally increased from a previousprogramming pulse wherein the program verify operation is performedafter each programming pulse.
 11. The method of claim 8 wherein biasingthe memory cell with the ramped voltage signal comprises biasing a wordline coupled to a control gate of a plurality of memory cells.
 12. Themethod of claim 8 wherein both the digital representation of the rampedvoltage signal comprises a plurality of digital data each representing adifferent voltage of the ramped voltage signal.
 13. A memory devicecomprising: an array of memory cells; a ramped voltage signal generatorconfigured to generate a ramped voltage signal comprising a plurality ofvoltages, the ramped voltage signal generator coupled to control gatesof memory cells of the array of memory cells; an analog-to-digitalconverter coupled to the ramped voltage signal generator and configuredto generate a digital representation of each of the plurality ofvoltages; latches configured to store target data during a programverify operation of a memory cell, the target data indicative of datastored in the memory cell; and a greater-than-or-equal-to circuitcoupled to the array of memory cells that is configured to generate averify indication signal during the program verify operation when adigital representation of a voltage that activates the memory cell isgreater than or equal to the target data.
 14. The memory device of claim13 wherein the array of memory cells comprises one of single level cellsor multilevel cells.
 15. The memory device of claim 13 wherein thegreater-than-or-equal-to circuit comprises: a plurality of equal-tocomparison circuits configured to generate the verify indication signalonly when the digital representation of the voltage that activates thememory cell is equal to the target data; and a plurality of greater-thancomparison circuits coupled to the comparison circuit only when thedigital representation of the voltage that activates the memory cell isgreater than the target data.
 16. The memory device of claim 15 whereinthe plurality of equal-to comparison circuits and the plurality ofgreater-than comparison circuits are bit comparison circuits.
 17. Thememory device of claim 15 wherein the plurality of equal-to comparisoncircuits and the plurality of greater-than comparison circuits areconfigured to perform most-significant bit to least significant bitcomparison on a bit-by-bit comparison.
 18. The memory device of claim 13and further comprising a sense amplifier that enables thegreater-than-or-equal-to circuit in response to the activation of thememory cell.
 19. The memory device of claim 15 wherein all of theplurality of equal-to comparison circuits are configured to be turned onwhen the digital representation of the voltage that activates the memorycell is equal to the target data.
 20. The memory device of claim 19wherein the plurality of greater-than circuits are configured to beturned off when the digital representation of the voltage that activatesthe memory cell is equal to the target data.